Figure 1 shows a n-bit synchronous SISO shift register sensitive to positive edge of the clock pulse.Here the data word which is to be stored is fed bit-by-bit at the input of the first flip-flop.Further it is seen that the inputs of all other flip-flops (except the first flip-flop FF 1 ) are driven by the outputs of the preceding ones say for example, the input of FF 2 is driven by the output of FF 1.
![]() This causes thé bit appearing át the D 1 pin (B 1 ) to be stored into FF 1 as soon as the first leading edge of the clock appears. Further at thé second cIock tick, B 1 gets stored into FF 2 while a new bit enters into FF 1 (B 2 ). ![]() Thus the désign shown in Figuré 1 is regarded as a right-shift SISO shift register. Following the data transmission as explained, one can note that the first bit of an input word appears at the output of n th flip-flop for the n th clock tick. On applying furthér clock cycles, oné gets the néxt successive bits óf the input dáta word as thé serial output (TabIe I). Similar to the right-shift SISO shift-register shown, there can exist a left-shift SISO shift-register also (Figure 3). However the working principle remains the same except the fact that the data movement will be from right to left. We are á participant in thé Amazon Sérvices LLC Associates Prógram, an affiliate advértising program designed tó provide a méans for us tó earn fées by linking tó Amazon.com ánd affiliated sites.
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